國立交通大學電子工程系人才培訓中心

    The growing needs of efficient data transmission and storage drive the information delivery technology to a new frontier recently. Either in the new radio (NR) links of 5G communications, or in the emerging non-volatile memories (NVMs) with continuously increasing capacity, error correcting codes (ECCs) are essential and crucial in maintaining the data correctness.
    In this talk, we will cover major ECC design and architecture, including over Gb/s LDPC-BC, energy-efficient LDPC-CC, and Polar/Turbo decoders that fulfill different requirements in various 5G scenarios. For NVM applications, we will introduce 1-error and 2-error correcting scheme with parallel architecture for NOR flash, as well as BCH and LDPC coding scheme for NAND/3D-NAND, to address low-latency and high-throughput solutions.